Miniaturization of electronic products and IC chips is an important trend in the development of semiconductor technology. Configurable integrated circuits that are currently available in the market (e.g. field programmable gate array (FPGA) or other types) have different internal connection structures and different designs of internal configurable logic block (CLB) types. Generally speaking, a CLB is equipped with a memory inside. The memory can serve as a look-up table (LUT). That is, the user may write a truth table (i.e. relationship between input and output) in the memory, so as to equip the CLB with a corresponding function (e.g. logic gate, adder, subtractor, or other functions). Because fabricating processes vary greatly between different memory types, there is difficulty in integrating system-on-a-chip (SoC), and this is a challenge to the development of embedded memory. In terms of fabricating process, for example, a flash memory element requires additional two to eight masks in comparison with a static random access memory (SRAM) element and may require new fabricating processes. Thus, the difficulty and costs of integration of SoC are increased.
The conventional CLB uses SRAM to store the LUT. Due to different contents of the LUT, the CLB may have different logic operation functions. However, when the system power is interrupted, the programming content (LUT content) stored by the SRAM will disappear. For this reason, the programming system has to rewrite the programming content from an external memory device into the SRAM in the LUT whenever the system voltage resumes. Consequently, the starting process of the CLB is complicated and the costs are increased. In addition to the above, CLB equipped with SRAM usually has higher static power consumption and dynamic power consumption.